1. Field of the Invention
This invention relates to computer circuitry and, more particularly, to apparatus for providing signals for testing the condition of computer circuitry.
2. History of the Prior Art
Computer circuitry becomes more and more complicated with each new improvement devised. For example, microprocessors used for desktop computers now include over a million transistors in a single integrated circuit, and more advanced processors presently in the planning stage are expected to include approximately three million transistors. With this very large number of components, the number of manufacturing defects which may cause circuit errors becomes very large. Consequently, it is necessary to subject these circuits to extensive testing prior to their release for sale and use.
The typical manner in which testing has been accomplished in prior art arrangements, is that one or more special signals are provided to one or more of the external address pins of the circuit being tested. Typically, these signals are at a higher voltage than is used for normal operating signals applied to such pins. This allows the test modes to be hidden from the typical user. The signals used for generating any particular test cause centralized circuitry within the circuit being tested to detect and decode the particular signals and generate all of the internal signals necessary for the particular test. Thus, if the characteristics of a memory array are being tested to see if the components of particular columns leak current, high voltage input signals would be applied to a few pins and detected by circuitry on the chip being tested. This would cause the centralized circuitry to generate signals which cause the bit lines of the array to be connected to external pins so that the results could be measured, other signals which cause all or a particular column of the array to be selected, and signals which cause the word lines to be turned off. These signals would produce the circuit conditions in which external signals could be provided to the array to generate results which may be measured to determine whether the particular aspect being tested is functioning correctly.
A number of problems arise from such prior art testing methods. First, there are a limited number of pins available at any time which may be used for receiving the high voltage signals to initiate the various test modes. A large number of the pins must be used for their normal purposes in order to generate the conditions being tested. For example, the pins used in addressing a particular column cannot be used for the high voltage signals to set up the tests because they must be used in the test mode to select the column to be tested. Thus, while integrated circuits have become more complex and require more testing, the pins available for this purpose have decreased. Second, the method of generating a series of signals within the circuitry being tested in response to a high voltage signal on one or a few external pins requires that centralized decoding circuitry be provided on the chip for determining the particular test required and generating all of the signals to be utilized in setting up the test conditions. Moreover, the signals produced by such circuitry must be bused from the centralized decoding circuitry throughout the circuitry being tested. This requires quite complicated decoding circuitry and very large complicated busing paths for the test signals. As the number of tests to be run increases, the size and complexity of the decoding circuitry becomes overwhelming. An additional problem of the prior art test circuitry is that requiring that all of the signals used by a particular test be produced in response to a single set of external signals means that only the test modes designed into the decoding circuitry can be utilized once the chip is designed.
It is very desirable that some arrangement be provided for testing complex integrated circuitry which allows a great number of different tests to be provided without increasing the complication of the testing circuitry. Moreover, it is desirable that new test modes be possible even though the circuitry including the test circuitry has already been designed and incorporated within the circuitry to be tested. It is also desirable that all of this be accomplished while actually reducing the complexity of the testing circuitry.